The present invention generally relates to semiconductor devices and more particularly to a ultrafine high-speed semiconductor device having a high dielectric or so-called high-K dielectric film.
In recent ultrahigh-speed semiconductor devices, the gate length of 0.1 μm or less is becoming possible with advancement of ultrafine processing technology. Generally, the operational speed of a semiconductor device is improved with device miniaturization, while there is a need in such highly miniaturized semiconductor device to decrease the thickness of the gate insulation film with reduction of gate length caused by device miniaturization.
In the case the gate length has become 0.1 μm or less, on the other hand, it becomes necessary to set the thickness of the gate insulation film to 1-2nm or less in the case an SiO2 film is used for the gate insulation film. In such a very thin gate insulation film, on the other hand, there occurs increase of tunneling current, and as a result, there arises the problem of increase of gate leakage current.
In view of the situations noted above, there has been a proposal to use a high-K dielectric material, such as Ta2O5, Al2O3, ZrO2, HfO2, ZrSiO4, HfSiO4, and the like, characterized by a small SiO2- equivalent thickness even in the case the film has a large physical thickness, for the gate insulation film. By using such a high-K dielectric film, it becomes possible to use a physical thickness of about 10 nm even in the case of ultrahigh-speed semiconductor devices in which the gate length is reduced to 0.1 μm or less, and the gate leakage current caused by tunneling effect is suppressed.
In a semiconductor device that uses such high-K dielectric film for the gate insulation film, it is preferable to form the high-K dielectric film directly on the Si substrate for reducing the SiO2 equivalent thickness of the insulation film. On the other hand, in the case such a high-K dielectric film is formed directly on a Si substrate, there is caused diffusion of metal element from the high-K dielectric film into the Si substrate, and there is caused the problem of carrier scattering in the channel region.
From the viewpoint of improving the carrier mobility in the channel region, it is preferable to interpose a very thin base oxide film between the high-K gate oxide film and the Si substrate with the thickness of 1 nm or less, preferably 0.8 nm or less. This base oxide film has to be very thin. Otherwise, the effect of using the high-K dielectric film for the gate insulation film would be canceled out.
FIGS. 1A-1C show a conventional fabrication process of a semiconductor device that has a high-K dielectric gate insulation film.
Referring to FIG. 1A, a base oxide film 12 of a very thin SiO2 film preferably having a thickness of 1 nm or less is formed on a silicon substrate 11 for example by a radical oxidation processing that uses ultraviolet-excited oxygen radicals. Next, in the step of FIG. 1B, a metal oxide film 13 of HfO2 or ZrO2 is formed on the base oxide film 12 by an atomic layer deposition (ALD) process, metal organic chemical vapor deposition (MOCVD) process, or the like.
In the step of FIG. 1A, the radical oxidation processing may be conducted according to the process described in Japanese Laid-Open Patent Publication 2002-100627, which is incorporated herein as reference. As a result of oxidation of the silicon substrate by the ultraviolet-excited radicals, it becomes possible to form the base oxide film having a thickness corresponding to 2-3 molecular layers stably and with excellent reproducibility. Further, by using the foregoing method disclosed in the Japanese Laid-Open Patent Publication 2002-100627, it is also possible to obtain a silicon oxynitride film for the base oxide film 12 by introducing nitrogen atoms into the extremely thin silicon oxide film thus formed.
In the step of FIG. 1B, the deposition of the metal oxide film 13 may be conducted by the ALD process disclosed in Japanese Laid-Open Patent Publication 2002-151489 or by an MOCVD process.
Meanwhile, it is necessary that the metal oxide film 13 formed as a high-K dielectric film is crystallized, contrary to the case of amorphous SiO2 film, in order to exploit the performance of the high-K dielectric film. Thus, it has been practiced to apply a thermal annealing process to the structure obtained in the step of FIG. 1B as represented in FIG.1C for crystallizing the metal oxide film 13. As the metal oxide film 12 is formed on the amorphous base oxide film 12, the metal oxide film 13 becomes a polycrystalline body when crystallized. Such crystallized metal oxide film 13 is used for the high-K dielectric gate insulation film of high-speed semiconductor devices.
As explained previously, it is required that the base oxide film 12 formed at the interface between the high-K dielectric gate insulation film and the silicon substrate has as small thickness as possible. In the case the thickness of the base oxide film 12 is increased, the effect of using the high-K gate insulation film 13 is canceled out.
Meanwhile, in the deposition step of the metal oxide film 13 of FIG. 1B, it should be noted that the process is conducted in an oxygen atmosphere particularly in the case an MOCVD process is used. Thus, in the case the substrate temperature is high at the time of the deposition process, there is a substantial risk that the thickness of the base oxide film may increase as a result of oxidation of the substrate. Further, the thickness of the base oxide film 12 may increase also in the crystallization annealing step of FIG. 1C.
Further, in the step of FIG. 1C, there is caused grain growth in the microcrystals in the metal oxide film 13 at the time of crystallization of the metal oxide film 13, while such a grain growth caused in the film 13 may invite the problem of formation of irregular or unstable interface with respect to the underlying base oxide film. Formation of such irregular or unstable interface invites the problem of increase of gate leakage current.